Memory devices are becoming more popular and correspondingly an increasing request for devices with larger density is present. One approach to address this need is to produce highly compact memory devices with the most advanced technology, so as to reduce the overall unit cost. Memories with NAND architecture are very compact and therefore ideal for the production of high density memory devices.
With the progress of technology, increasingly smaller features sizes are achievable, both in terms of line width and spacing, as well as the minimum dimension of elementary components. Such a continuous miniaturization process in silicon-based technologies emphasizes some limitations that were not relevant in past generations. For example, the functionality of NAND devices becomes less reliable because of programming disturbances that affect word lines that are spaced apart by very small distances.
Moreover, the manufacturing process control becomes so stringent that it becomes difficult to create memory cells with the same performances, especially when they are near to a border or to a non-periodic feature of a memory array. In present day NAND memory devices, the immediate neighborhood of memory cells closest to the source selection and drain selection lines are different from all other memory cells in the NAND string. It is extremely difficult to account for such a difference in a controlled way, therefore the electrical behavior of these memory cells may differ from all others and create undesired functions of the electronic NAND memory devices.